1. Field of the Invention
The present invention relates to a DMA (direct memory access) controller, and more specifically to a DMA controller capable of continuously carrying out a DMA transfer while automatically setting either or both of a transfer size and a transfer destination address.
2. Description of Related Art
In a typical one of conventional DMA controllers, a transfer size register and a transfer address register are written with set values from a CPU (central processing unit), respectively. When a DMA transfer is started, the set value of the transfer size register is loaded to a transfer size counter, and the set value of the transfer destination address register is loaded to a transfer destination address counter, so that the DMA transfer is carried out using the values of the transfer size counter and the transfer destination address counter.
During a period of time after a first DMA transfer was completed and before a next DMA transfer is started, if the DMA controller were controlled by the CPU so as to set the transfer size register with a transfer size of the next DMA transfer and also to set the transfer destination address register with a transfer destination head address of the next DMA transfer, overhead inevitably occurs. In order to minimize this overhead, an auto-initialize operation has been proposed, in which, during a period of time in which the first DMA transfer is being executed, the CPU controls writes the transfer size and the transfer destination head address of the next DMA transfer into the transfer size register and the transfer destination address register, respectively, and when the first DMA transfer is completed, the set values of the transfer size register and the transfer destination address register are automatically loaded to the transfer size counter and the transfer destination address counter, respectively, so that the next DMA transfer is continuously carried out.
In the above mentioned auto-initialized operation of the conventional DMA controller, it is necessary that, during a period from the start to the completion of one DMA transfer, the CPU sets the transfer size register and the transfer destination address register for a next DMA transfer. However, if new values for a new DMA transfer have not been set to these registers until the DMA transfer being executed is completed, because of various factors such as CPU interrupt processings and a priority order between the DMA controller and the CPU, the values of the transfer size register and the transfer destination address register are loaded to the transfer size counter and the transfer destination address counter, respectively, regardless of whether or not the new values for a new DMA transfer have been set to the transfer size register and the transfer destination address register. In this case, the values of the transfer size counter and the transfer destination address counter are wrong, and therefore, the transfer data number and the transfer destination address cannot be ensured in the next DMA transfer.